cnc.info.pl - FORUM CNC

markcomp77

poorchava pisze:Stellaris

ma jedne z najlepszych not do zastosowań silnikowych
ale pewien lęk budzą informacje z netu dotyczące dużej ilości błędów w samym armie stellarisa

[ Dodano: 2012-10-17, 15:41 ]

poorchava pisze: ostrzę zęby na płytkę ewaluacyjną z LPC4300

fajne... za dużo robią tych ARMów aby je poznać wszystkie
czuję się jak łakomczuch w cukierni - wszystkie by zjadł... ale nie wszystkie się zmieszczą

w jaki sposób działa ta multiprocesorowość w LPC4300
są dwie jednostki CPU: M4 i M0... magistrala i zasoby...
czy zasoby są dzielone?
czy są jakieś semafory ?..itd...

może jakaś życzliwa dusza opisała by to w paru słowach?

[ Dodano: 2012-10-17, 21:29 ]

The Cortex-M0 co-processor off-loads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core.

z tego wynika, że ta wielozadaniowość dla podwójnego CPU jest asymetryczna
jeden procek M0 - słabszy robi przy transferach
mocniejszy M4 - jest to zadań obliczeniowych...

markcomp77

timer do rozpracowania.. też mnie interesuje
jakieś niby wprowadzenie na tego temat jest na stronie kamami pod nazwą stm32.eu (chyba) - trzeba się logować... to samo było w praktycznej elektronice
to jest tylko przegląd właściwie... ale zawsze to już coś

na początek - skupiając się na LEDzie-- można by zrobić mrugające ledy za pomocą timera (pwm)

markcomp77

blue_17 pisze:http://www.sunduino.neth.pl/

Tu jest cały kurs discovery ale z rdzeniem F0 ale wszystko opisane zakładka ARM i Discovery

ale schowany..
jednak się dokopałem:
http://sunriver.psp29.anv.pl/index.php/ ... /discovery

dzięks...

markcomp77

a ja już widzę, że tę liblotekę będę używał

no i zbieram się, za analizę timer.h

fancyblink.list zapewnie wyjaśni wątpliwości, gdzie co ustawione (i jak)

Kod: Zaznacz cały


fancyblink.elf:     file format elf32-littlearm


Disassembly of section .text: 

08000000 <vector_table>: 
 8000000:	00 00 02 20 e5 01 00 08 37 02 00 08 35 02 00 08     ... ....7...5...
 8000010:	35 02 00 08 35 02 00 08 35 02 00 08 00 00 00 00     5...5...5.......
	...
 800002c:	37 02 00 08 37 02 00 08 00 00 00 00 37 02 00 08     7...7.......7...
 800003c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800004c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800005c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800006c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800007c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800008c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800009c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 80000ac:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 80000bc:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 80000cc:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 80000dc:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 80000ec:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 80000fc:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800010c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800011c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800012c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800013c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800014c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800015c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800016c:	37 02 00 08 37 02 00 08 37 02 00 08 37 02 00 08     7...7...7...7...
 800017c:	37 02 00 08 37 02 00 08                             7...7...

08000184 <clock_setup>: 
#include <libopencm3/stm32/f4/rcc.h> 
#include <libopencm3/stm32/f4/gpio.h> 

/* Set STM32 to 168 MHz. */
void clock_setup(void) 
{ 
 8000184:	b508      	push	{r3, lr} 
	rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]); 
 8000186:	4804      	ldr	r0, [pc, #16]	; (8000198 <clock_setup+0x14>) 
 8000188:	f000 f8fa 	bl	8000380 <rcc_clock_setup_hse_3v3> 

	/* Enable GPIOD clock. */
	rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN); 
 800018c:	4803      	ldr	r0, [pc, #12]	; (800019c <clock_setup+0x18>) 
 800018e:	2108      	movs	r1, #8
} 
 8000190:	e8bd 4008 	ldmia.w	sp!, {r3, lr} 
void clock_setup(void) 
{ 
	rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]); 

	/* Enable GPIOD clock. */
	rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN); 
 8000194:	f000 b8b8 	b.w	8000308 <rcc_peripheral_enable_clock> 
 8000198:	080004a4 	.word	0x080004a4
 800019c:	40023830 	.word	0x40023830

080001a0 <gpio_setup>: 
} 

void gpio_setup(void) 
{ 
	/* Set GPIO12-15 (in GPIO port D) to 'output push-pull'. */
	gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT,
 80001a0:	4803      	ldr	r0, [pc, #12]	; (80001b0 <gpio_setup+0x10>) 
 80001a2:	2101      	movs	r1, #1
 80001a4:	2200      	movs	r2, #0
 80001a6:	f44f 4370 	mov.w	r3, #61440	; 0xf000
 80001aa:	f000 b929 	b.w	8000400 <gpio_mode_setup> 
 80001ae:	bf00      	nop
 80001b0:	40020c00 	.word	0x40020c00

080001b4 <main>: 
			GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15); 
} 

int main(void) 
{ 
 80001b4:	b508      	push	{r3, lr} 
	int i; 

	clock_setup(); 
 80001b6:	f7ff ffe5 	bl	8000184 <clock_setup> 
	gpio_setup(); 
 80001ba:	f7ff fff1 	bl	80001a0 <gpio_setup> 

	/* Set two LEDs for wigwag effect when toggling. */
	gpio_set(GPIOD, GPIO12 | GPIO14); 
 80001be:	4807      	ldr	r0, [pc, #28]	; (80001dc <main+0x28>) 
 80001c0:	f44f 41a0 	mov.w	r1, #20480	; 0x5000
 80001c4:	f000 f93f 	bl	8000446 <gpio_set> 

	/* Blink the LEDs (PD12, PD13, PD14 and PD15) on the board. */
	while (1) { 
		/* Toggle LEDs. */
		gpio_toggle(GPIOD, GPIO12 | GPIO13 | GPIO14 | GPIO15); 
 80001c8:	4804      	ldr	r0, [pc, #16]	; (80001dc <main+0x28>) 
 80001ca:	f44f 4170 	mov.w	r1, #61440	; 0xf000
 80001ce:	f000 f93c 	bl	800044a <gpio_toggle> 
 80001d2:	4b03      	ldr	r3, [pc, #12]	; (80001e0 <main+0x2c>) 
		for (i = 0; i < 6000000; i++) /* Wait a bit. */
			__asm__("nop"); 
 80001d4:	bf00      	nop

	/* Blink the LEDs (PD12, PD13, PD14 and PD15) on the board. */
	while (1) { 
		/* Toggle LEDs. */
		gpio_toggle(GPIOD, GPIO12 | GPIO13 | GPIO14 | GPIO15); 
		for (i = 0; i < 6000000; i++) /* Wait a bit. */
 80001d6:	3b01      	subs	r3, #1
 80001d8:	d1fc      	bne.n	80001d4 <main+0x20> 
 80001da:	e7f5      	b.n	80001c8 <main+0x14> 
 80001dc:	40020c00 	.word	0x40020c00
 80001e0:	005b8d80 	.word	0x005b8d80

080001e4 <reset_handler>: 

void reset_handler(void) 
{ 
	volatile unsigned *src, *dest; 

	__asm__("MSR msp, %0" : : "r"(&_stack)); 
 80001e4:	4b0d      	ldr	r3, [pc, #52]	; (800021c <reset_handler+0x38>) 
 80001e6:	f383 8808 	msr	MSP, r3

	/* Enable access to Floating-Point coprocessor. */
	SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); 
 80001ea:	4b0d      	ldr	r3, [pc, #52]	; (8000220 <reset_handler+0x3c>) 
	dcmi_isr,
	cryp_isr,
	hash_rng_isr,
}; 

void reset_handler(void) 
 80001ec:	490d      	ldr	r1, [pc, #52]	; (8000224 <reset_handler+0x40>) 
	volatile unsigned *src, *dest; 

	__asm__("MSR msp, %0" : : "r"(&_stack)); 

	/* Enable access to Floating-Point coprocessor. */
	SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); 
 80001ee:	681a      	ldr	r2, [r3, #0] 
 80001f0:	f442 0270 	orr.w	r2, r2, #15728640	; 0xf00000
 80001f4:	601a      	str	r2, [r3, #0] 

	for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) 
 80001f6:	4b0c      	ldr	r3, [pc, #48]	; (8000228 <reset_handler+0x44>) 
 80001f8:	4a0c      	ldr	r2, [pc, #48]	; (800022c <reset_handler+0x48>) 
	dcmi_isr,
	cryp_isr,
	hash_rng_isr,
}; 

void reset_handler(void) 
 80001fa:	1ac9      	subs	r1, r1, r3
	__asm__("MSR msp, %0" : : "r"(&_stack)); 

	/* Enable access to Floating-Point coprocessor. */
	SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); 

	for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) 
 80001fc:	e002      	b.n	8000204 <reset_handler+0x20> 
		*dest = *src; 
 80001fe:	5858      	ldr	r0, [r3, r1] 
 8000200:	f843 0b04 	str.w	r0, [r3], #4
	__asm__("MSR msp, %0" : : "r"(&_stack)); 

	/* Enable access to Floating-Point coprocessor. */
	SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); 

	for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) 
 8000204:	4293      	cmp	r3, r2
 8000206:	d3fa      	bcc.n	80001fe <reset_handler+0x1a> 
 8000208:	e002      	b.n	8000210 <reset_handler+0x2c> 
		*dest = *src; 

	while (dest < &_ebss) 
		*dest++ = 0; 
 800020a:	f843 2b04 	str.w	r2, [r3], #4
 800020e:	e001      	b.n	8000214 <reset_handler+0x30> 
	SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); 

	for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) 
		*dest = *src; 

	while (dest < &_ebss) 
 8000210:	4907      	ldr	r1, [pc, #28]	; (8000230 <reset_handler+0x4c>) 
		*dest++ = 0; 
 8000212:	2200      	movs	r2, #0
	SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); 

	for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) 
		*dest = *src; 

	while (dest < &_ebss) 
 8000214:	428b      	cmp	r3, r1
 8000216:	d3f8      	bcc.n	800020a <reset_handler+0x26> 
		*dest++ = 0; 

	/* Call the application's entry point. */
	main(); 
 8000218:	f7ff bfcc 	b.w	80001b4 <main> 
 800021c:	20020000 	.word	0x20020000
 8000220:	e000ed88 	.word	0xe000ed88
 8000224:	080004bc 	.word	0x080004bc
 8000228:	20000000 	.word	0x20000000
 800022c:	20000008 	.word	0x20000008
 8000230:	20000008 	.word	0x20000008

08000234 <blocking_handler>: 
} 

void blocking_handler(void) 
{ 
 8000234:	e7fe      	b.n	8000234 <blocking_handler> 

08000236 <null_handler>: 
} 

void null_handler(void) 
{ 
	/* Do nothing. */
} 
 8000236:	4770      	bx	lr

08000238 <rcc_wait_for_osc_ready>: 
	return ((RCC_CIR & RCC_CIR_CSSF) != 0); 
} 

void rcc_wait_for_osc_ready(osc_t osc) 
{ 
	switch (osc) { 
 8000238:	2804      	cmp	r0, #4
 800023a:	d81c      	bhi.n	8000276 <rcc_wait_for_osc_ready+0x3e> 
 800023c:	e8df f000 	tbb	[pc, r0] 
 8000240:	120d0803 	.word	0x120d0803
 8000244:	17          	.byte	0x17
 8000245:	00          	.byte	0x00
	case PLL: 
		while ((RCC_CR & RCC_CR_PLLRDY) == 0); 
 8000246:	4b0c      	ldr	r3, [pc, #48]	; (8000278 <rcc_wait_for_osc_ready+0x40>) 
 8000248:	681a      	ldr	r2, [r3, #0] 
 800024a:	0191      	lsls	r1, r2, #6
 800024c:	d5fc      	bpl.n	8000248 <rcc_wait_for_osc_ready+0x10> 
 800024e:	4770      	bx	lr
		break; 
	case HSE: 
		while ((RCC_CR & RCC_CR_HSERDY) == 0); 
 8000250:	4b09      	ldr	r3, [pc, #36]	; (8000278 <rcc_wait_for_osc_ready+0x40>) 
 8000252:	681a      	ldr	r2, [r3, #0] 
 8000254:	0392      	lsls	r2, r2, #14
 8000256:	d5fc      	bpl.n	8000252 <rcc_wait_for_osc_ready+0x1a> 
 8000258:	4770      	bx	lr
		break; 
	case HSI: 
		while ((RCC_CR & RCC_CR_HSIRDY) == 0); 
 800025a:	4b07      	ldr	r3, [pc, #28]	; (8000278 <rcc_wait_for_osc_ready+0x40>) 
 800025c:	681a      	ldr	r2, [r3, #0] 
 800025e:	0790      	lsls	r0, r2, #30
 8000260:	d5fc      	bpl.n	800025c <rcc_wait_for_osc_ready+0x24> 
 8000262:	4770      	bx	lr
		break; 
	case LSE: 
		while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); 
 8000264:	4b05      	ldr	r3, [pc, #20]	; (800027c <rcc_wait_for_osc_ready+0x44>) 
 8000266:	681a      	ldr	r2, [r3, #0] 
 8000268:	0791      	lsls	r1, r2, #30
 800026a:	d5fc      	bpl.n	8000266 <rcc_wait_for_osc_ready+0x2e> 
 800026c:	4770      	bx	lr
		break; 
	case LSI: 
		while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); 
 800026e:	4b04      	ldr	r3, [pc, #16]	; (8000280 <rcc_wait_for_osc_ready+0x48>) 
 8000270:	681a      	ldr	r2, [r3, #0] 
 8000272:	0792      	lsls	r2, r2, #30
 8000274:	d5fc      	bpl.n	8000270 <rcc_wait_for_osc_ready+0x38> 
 8000276:	4770      	bx	lr
 8000278:	40023800 	.word	0x40023800
 800027c:	40023870 	.word	0x40023870
 8000280:	40023874 	.word	0x40023874

08000284 <rcc_wait_for_sysclk_status>: 
	} 
} 

void rcc_wait_for_sysclk_status(osc_t osc) 
{ 
	switch (osc) { 
 8000284:	2801      	cmp	r0, #1
 8000286:	d00a      	beq.n	800029e <rcc_wait_for_sysclk_status+0x1a> 
 8000288:	d302      	bcc.n	8000290 <rcc_wait_for_sysclk_status+0xc> 
 800028a:	2802      	cmp	r0, #2
 800028c:	d112      	bne.n	80002b4 <rcc_wait_for_sysclk_status+0x30> 
 800028e:	e00d      	b.n	80002ac <rcc_wait_for_sysclk_status+0x28> 
	case PLL: 
		while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); 
 8000290:	4b09      	ldr	r3, [pc, #36]	; (80002b8 <rcc_wait_for_sysclk_status+0x34>) 
 8000292:	681a      	ldr	r2, [r3, #0] 
 8000294:	f002 0203 	and.w	r2, r2, #3
 8000298:	2a02      	cmp	r2, #2
 800029a:	d1fa      	bne.n	8000292 <rcc_wait_for_sysclk_status+0xe> 
 800029c:	4770      	bx	lr
		break; 
	case HSE: 
		while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); 
 800029e:	4b06      	ldr	r3, [pc, #24]	; (80002b8 <rcc_wait_for_sysclk_status+0x34>) 
 80002a0:	681a      	ldr	r2, [r3, #0] 
 80002a2:	f002 0203 	and.w	r2, r2, #3
 80002a6:	2a01      	cmp	r2, #1
 80002a8:	d1fa      	bne.n	80002a0 <rcc_wait_for_sysclk_status+0x1c> 
 80002aa:	4770      	bx	lr
		break; 
	case HSI: 
		while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); 
 80002ac:	4b02      	ldr	r3, [pc, #8]	; (80002b8 <rcc_wait_for_sysclk_status+0x34>) 
 80002ae:	681a      	ldr	r2, [r3, #0] 
 80002b0:	0790      	lsls	r0, r2, #30
 80002b2:	d1fc      	bne.n	80002ae <rcc_wait_for_sysclk_status+0x2a> 
 80002b4:	4770      	bx	lr
 80002b6:	bf00      	nop
 80002b8:	40023808 	.word	0x40023808

080002bc <rcc_osc_on>: 
	} 
} 

void rcc_osc_on(osc_t osc) 
{ 
	switch (osc) { 
 80002bc:	2804      	cmp	r0, #4
 80002be:	d81b      	bhi.n	80002f8 <rcc_osc_on+0x3c> 
 80002c0:	e8df f000 	tbb	[pc, r0] 
 80002c4:	0f0d0803 	.word	0x0f0d0803
 80002c8:	15          	.byte	0x15
 80002c9:	00          	.byte	0x00
	case PLL: 
		RCC_CR |= RCC_CR_PLLON; 
 80002ca:	4b0c      	ldr	r3, [pc, #48]	; (80002fc <rcc_osc_on+0x40>) 
 80002cc:	681a      	ldr	r2, [r3, #0] 
 80002ce:	f042 7280 	orr.w	r2, r2, #16777216	; 0x1000000
 80002d2:	e00a      	b.n	80002ea <rcc_osc_on+0x2e> 
		break; 
	case HSE: 
		RCC_CR |= RCC_CR_HSEON; 
 80002d4:	4b09      	ldr	r3, [pc, #36]	; (80002fc <rcc_osc_on+0x40>) 
 80002d6:	681a      	ldr	r2, [r3, #0] 
 80002d8:	f442 3280 	orr.w	r2, r2, #65536	; 0x10000
 80002dc:	e005      	b.n	80002ea <rcc_osc_on+0x2e> 
		break; 
	case HSI: 
		RCC_CR |= RCC_CR_HSION; 
 80002de:	4b07      	ldr	r3, [pc, #28]	; (80002fc <rcc_osc_on+0x40>) 
 80002e0:	e000      	b.n	80002e4 <rcc_osc_on+0x28> 
		break; 
	case LSE: 
		RCC_BDCR |= RCC_BDCR_LSEON; 
 80002e2:	4b07      	ldr	r3, [pc, #28]	; (8000300 <rcc_osc_on+0x44>) 
 80002e4:	681a      	ldr	r2, [r3, #0] 
 80002e6:	f042 0201 	orr.w	r2, r2, #1
 80002ea:	601a      	str	r2, [r3, #0] 
		break; 
 80002ec:	4770      	bx	lr
	case LSI: 
		RCC_CSR |= RCC_CSR_LSION; 
 80002ee:	4b05      	ldr	r3, [pc, #20]	; (8000304 <rcc_osc_on+0x48>) 
 80002f0:	681a      	ldr	r2, [r3, #0] 
 80002f2:	f042 0201 	orr.w	r2, r2, #1
 80002f6:	601a      	str	r2, [r3, #0] 
 80002f8:	4770      	bx	lr
 80002fa:	bf00      	nop
 80002fc:	40023800 	.word	0x40023800
 8000300:	40023870 	.word	0x40023870
 8000304:	40023874 	.word	0x40023874

08000308 <rcc_peripheral_enable_clock>: 
	} 
} 

void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) 
{ 
	*reg |= en; 
 8000308:	6803      	ldr	r3, [r0, #0] 
 800030a:	430b      	orrs	r3, r1
 800030c:	6003      	str	r3, [r0, #0] 
} 
 800030e:	4770      	bx	lr

08000310 <rcc_set_sysclk_source>: 

void rcc_set_sysclk_source(u32 clk) 
{ 
	u32 reg32; 

	reg32 = RCC_CFGR; 
 8000310:	4b03      	ldr	r3, [pc, #12]	; (8000320 <rcc_set_sysclk_source+0x10>) 
 8000312:	681a      	ldr	r2, [r3, #0] 
	reg32 &= ~((1 << 1) | (1 << 0)); 
 8000314:	f022 0203 	bic.w	r2, r2, #3
	RCC_CFGR = (reg32 | clk); 
 8000318:	4302      	orrs	r2, r0
 800031a:	601a      	str	r2, [r3, #0] 
} 
 800031c:	4770      	bx	lr
 800031e:	bf00      	nop
 8000320:	40023808 	.word	0x40023808

08000324 <rcc_set_ppre2>: 

void rcc_set_ppre2(u32 ppre2) 
{ 
	u32 reg32; 

	reg32 = RCC_CFGR; 
 8000324:	4b03      	ldr	r3, [pc, #12]	; (8000334 <rcc_set_ppre2+0x10>) 
 8000326:	681a      	ldr	r2, [r3, #0] 
	reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); 
 8000328:	f422 4260 	bic.w	r2, r2, #57344	; 0xe000
	RCC_CFGR = (reg32 | (ppre2 << 13)); 
 800032c:	ea42 3240 	orr.w	r2, r2, r0, lsl #13
 8000330:	601a      	str	r2, [r3, #0] 
} 
 8000332:	4770      	bx	lr
 8000334:	40023808 	.word	0x40023808

08000338 <rcc_set_ppre1>: 

void rcc_set_ppre1(u32 ppre1) 
{ 
	u32 reg32; 

	reg32 = RCC_CFGR; 
 8000338:	4b03      	ldr	r3, [pc, #12]	; (8000348 <rcc_set_ppre1+0x10>) 
 800033a:	681a      	ldr	r2, [r3, #0] 
	reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); 
 800033c:	f422 52e0 	bic.w	r2, r2, #7168	; 0x1c00
	RCC_CFGR = (reg32 | (ppre1 << 10)); 
 8000340:	ea42 2280 	orr.w	r2, r2, r0, lsl #10
 8000344:	601a      	str	r2, [r3, #0] 
} 
 8000346:	4770      	bx	lr
 8000348:	40023808 	.word	0x40023808

0800034c <rcc_set_hpre>: 

void rcc_set_hpre(u32 hpre) 
{ 
	u32 reg32; 

	reg32 = RCC_CFGR; 
 800034c:	4b03      	ldr	r3, [pc, #12]	; (800035c <rcc_set_hpre+0x10>) 
 800034e:	681a      	ldr	r2, [r3, #0] 
	reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); 
 8000350:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
	RCC_CFGR = (reg32 | (hpre << 4)); 
 8000354:	ea42 1200 	orr.w	r2, r2, r0, lsl #4
 8000358:	601a      	str	r2, [r3, #0] 
} 
 800035a:	4770      	bx	lr
 800035c:	40023808 	.word	0x40023808

08000360 <rcc_set_main_pll_hse>: 
		(pllq << RCC_PLLCFGR_PLLQ_SHIFT); 
} 

void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) 
{ 
	RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
 8000360:	f440 0080 	orr.w	r0, r0, #4194304	; 0x400000
		(plln << RCC_PLLCFGR_PLLN_SHIFT) |
 8000364:	ea40 1081 	orr.w	r0, r0, r1, lsl #6
		(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
 8000368:	0852      	lsrs	r2, r2, #1
		RCC_PLLCFGR_PLLSRC |
 800036a:	ea40 6003 	orr.w	r0, r0, r3, lsl #24

void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) 
{ 
	RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
		(plln << RCC_PLLCFGR_PLLN_SHIFT) |
		(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
 800036e:	3a01      	subs	r2, #1
		(pllq << RCC_PLLCFGR_PLLQ_SHIFT); 
} 

void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) 
{ 
	RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
 8000370:	4b02      	ldr	r3, [pc, #8]	; (800037c <rcc_set_main_pll_hse+0x1c>) 
		(plln << RCC_PLLCFGR_PLLN_SHIFT) |
		(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
		RCC_PLLCFGR_PLLSRC |
 8000372:	ea40 4002 	orr.w	r0, r0, r2, lsl #16
		(pllq << RCC_PLLCFGR_PLLQ_SHIFT); 
} 

void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) 
{ 
	RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
 8000376:	6018      	str	r0, [r3, #0] 
		(plln << RCC_PLLCFGR_PLLN_SHIFT) |
		(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
		RCC_PLLCFGR_PLLSRC |
		(pllq << RCC_PLLCFGR_PLLQ_SHIFT); 
} 
 8000378:	4770      	bx	lr
 800037a:	bf00      	nop
 800037c:	40023804 	.word	0x40023804

08000380 <rcc_clock_setup_hse_3v3>: 
	/* Return the clock source which is used as system clock. */
	return ((RCC_CFGR & 0x000c) >> 2); 
} 

void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) 
{ 
 8000380:	b510      	push	{r4, lr} 
 8000382:	4604      	mov	r4, r0
	/* Enable internal high-speed oscillator. */
	rcc_osc_on(HSI); 
 8000384:	2002      	movs	r0, #2
 8000386:	f7ff ff99 	bl	80002bc <rcc_osc_on> 
	rcc_wait_for_osc_ready(HSI); 
 800038a:	2002      	movs	r0, #2
 800038c:	f7ff ff54 	bl	8000238 <rcc_wait_for_osc_ready> 

	/* Select HSI as SYSCLK source. */
	rcc_set_sysclk_source(RCC_CFGR_SW_HSI); 
 8000390:	2000      	movs	r0, #0
 8000392:	f7ff ffbd 	bl	8000310 <rcc_set_sysclk_source> 

	/* Enable external high-speed oscillator 8MHz. */
	rcc_osc_on(HSE); 
 8000396:	2001      	movs	r0, #1
 8000398:	f7ff ff90 	bl	80002bc <rcc_osc_on> 
	rcc_wait_for_osc_ready(HSE); 
 800039c:	2001      	movs	r0, #1
 800039e:	f7ff ff4b 	bl	8000238 <rcc_wait_for_osc_ready> 

	/* Enable/disable high performance mode */
	if (!clock->power_save) 
 80003a2:	7be0      	ldrb	r0, [r4, #15] 
 80003a4:	b100      	cbz	r0, 80003a8 <rcc_clock_setup_hse_3v3+0x28> 
		pwr_set_vos_scale(SCALE1); 
	else
		pwr_set_vos_scale(SCALE2); 
 80003a6:	2001      	movs	r0, #1
 80003a8:	f000 f85e 	bl	8000468 <pwr_set_vos_scale> 

	/*
	 * Set prescalers for AHB, ADC, ABP1, ABP2.
	 * Do this before touching the PLL (TODO: why?).
	 */
	rcc_set_hpre(clock->hpre); 
 80003ac:	7b20      	ldrb	r0, [r4, #12] 
 80003ae:	f7ff ffcd 	bl	800034c <rcc_set_hpre> 
	rcc_set_ppre1(clock->ppre1); 
 80003b2:	7b60      	ldrb	r0, [r4, #13] 
 80003b4:	f7ff ffc0 	bl	8000338 <rcc_set_ppre1> 
	rcc_set_ppre2(clock->ppre2); 
 80003b8:	7ba0      	ldrb	r0, [r4, #14] 
 80003ba:	f7ff ffb3 	bl	8000324 <rcc_set_ppre2> 

	rcc_set_main_pll_hse(clock->pllm, clock->plln,
 80003be:	7922      	ldrb	r2, [r4, #4] 
 80003c0:	7963      	ldrb	r3, [r4, #5] 
 80003c2:	8861      	ldrh	r1, [r4, #2] 
 80003c4:	7820      	ldrb	r0, [r4, #0] 
 80003c6:	f7ff ffcb 	bl	8000360 <rcc_set_main_pll_hse> 
			     clock->pllp, clock->pllq); 

	/* Enable PLL oscillator and wait for it to stabilize. */
	rcc_osc_on(PLL); 
 80003ca:	2000      	movs	r0, #0
 80003cc:	f7ff ff76 	bl	80002bc <rcc_osc_on> 
	rcc_wait_for_osc_ready(PLL); 
 80003d0:	2000      	movs	r0, #0
 80003d2:	f7ff ff31 	bl	8000238 <rcc_wait_for_osc_ready> 

	/* Configure flash settings. */
	flash_set_ws(clock->flash_config); 
 80003d6:	68a0      	ldr	r0, [r4, #8] 
 80003d8:	f000 f83c 	bl	8000454 <flash_set_ws> 

	/* Select PLL as SYSCLK source. */
	rcc_set_sysclk_source(RCC_CFGR_SW_PLL); 
 80003dc:	2002      	movs	r0, #2
 80003de:	f7ff ff97 	bl	8000310 <rcc_set_sysclk_source> 

	/* Wait for PLL clock to be selected. */
	rcc_wait_for_sysclk_status(PLL); 
 80003e2:	2000      	movs	r0, #0
 80003e4:	f7ff ff4e 	bl	8000284 <rcc_wait_for_sysclk_status> 

	/* Set the peripheral clock frequencies used. */
	rcc_ppre1_frequency = clock->apb1_frequency; 
 80003e8:	6922      	ldr	r2, [r4, #16] 
 80003ea:	4b03      	ldr	r3, [pc, #12]	; (80003f8 <rcc_clock_setup_hse_3v3+0x78>) 
 80003ec:	601a      	str	r2, [r3, #0] 
	rcc_ppre2_frequency = clock->apb2_frequency; 
 80003ee:	6962      	ldr	r2, [r4, #20] 
 80003f0:	4b02      	ldr	r3, [pc, #8]	; (80003fc <rcc_clock_setup_hse_3v3+0x7c>) 
 80003f2:	601a      	str	r2, [r3, #0] 
} 
 80003f4:	bd10      	pop	{r4, pc} 
 80003f6:	bf00      	nop
 80003f8:	20000000 	.word	0x20000000
 80003fc:	20000004 	.word	0x20000004

08000400 <gpio_mode_setup>: 
 */

#include <libopencm3/stm32/f4/gpio.h> 

void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) 
{ 
 8000400:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr} 

	/*
	 * We want to set the config only for the pins mentioned in gpios,
	 * but keeping the others, so read out the actual config first.
	 */
	moder = GPIO_MODER(gpioport); 
 8000404:	6806      	ldr	r6, [r0, #0] 
	pupd = GPIO_PUPDR(gpioport); 
 8000406:	68c5      	ldr	r5, [r0, #12] 
 8000408:	2400      	movs	r4, #0

	for (i = 0; i < 16; i++) { 
		if (!((1 << i) & gpios)) 
			continue; 

		moder &= ~GPIO_MODE_MASK(i); 
 800040a:	f04f 0803 	mov.w	r8, #3
	 */
	moder = GPIO_MODER(gpioport); 
	pupd = GPIO_PUPDR(gpioport); 

	for (i = 0; i < 16; i++) { 
		if (!((1 << i) & gpios)) 
 800040e:	fa53 f704 	asrs.w	r7, r3, r4
 8000412:	f017 0f01 	tst.w	r7, #1
 8000416:	d00f      	beq.n	8000438 <gpio_mode_setup+0x38> 
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <libopencm3/stm32/f4/gpio.h> 

void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) 
 8000418:	0067      	lsls	r7, r4, #1

	for (i = 0; i < 16; i++) { 
		if (!((1 << i) & gpios)) 
			continue; 

		moder &= ~GPIO_MODE_MASK(i); 
 800041a:	fa08 fc07 	lsl.w	ip, r8, r7
 800041e:	ea6f 0c0c 	mvn.w	ip, ip
		moder |= GPIO_MODE(i, mode); 
 8000422:	fa01 f907 	lsl.w	r9, r1, r7

	for (i = 0; i < 16; i++) { 
		if (!((1 << i) & gpios)) 
			continue; 

		moder &= ~GPIO_MODE_MASK(i); 
 8000426:	ea0c 0606 	and.w	r6, ip, r6
		moder |= GPIO_MODE(i, mode); 
		pupd &= ~GPIO_PUPD_MASK(i); 
 800042a:	ea0c 0505 	and.w	r5, ip, r5
		pupd |= GPIO_PUPD(i, pull_up_down); 
 800042e:	fa12 f707 	lsls.w	r7, r2, r7
	for (i = 0; i < 16; i++) { 
		if (!((1 << i) & gpios)) 
			continue; 

		moder &= ~GPIO_MODE_MASK(i); 
		moder |= GPIO_MODE(i, mode); 
 8000432:	ea46 0609 	orr.w	r6, r6, r9
		pupd &= ~GPIO_PUPD_MASK(i); 
		pupd |= GPIO_PUPD(i, pull_up_down); 
 8000436:	433d      	orrs	r5, r7
 8000438:	3401      	adds	r4, #1
	 * but keeping the others, so read out the actual config first.
	 */
	moder = GPIO_MODER(gpioport); 
	pupd = GPIO_PUPDR(gpioport); 

	for (i = 0; i < 16; i++) { 
 800043a:	2c10      	cmp	r4, #16
 800043c:	d1e7      	bne.n	800040e <gpio_mode_setup+0xe> 
		pupd &= ~GPIO_PUPD_MASK(i); 
		pupd |= GPIO_PUPD(i, pull_up_down); 
	} 

	/* Set mode and pull up/down control registers. */
	GPIO_MODER(gpioport) = moder; 
 800043e:	6006      	str	r6, [r0, #0] 
	GPIO_PUPDR(gpioport) = pupd; 
 8000440:	60c5      	str	r5, [r0, #12] 
} 
 8000442:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc} 

08000446 <gpio_set>: 
	GPIO_AFRH(gpioport) = afrh; 
} 

void gpio_set(u32 gpioport, u16 gpios) 
{ 
	GPIO_BSRR(gpioport) = gpios; 
 8000446:	6181      	str	r1, [r0, #24] 
} 
 8000448:	4770      	bx	lr

0800044a <gpio_toggle>: 
	return gpio_port_read(gpioport) & gpios; 
} 

void gpio_toggle(u32 gpioport, u16 gpios) 
{ 
	GPIO_ODR(gpioport) ^= gpios; 
 800044a:	6943      	ldr	r3, [r0, #20] 
 800044c:	404b      	eors	r3, r1
 800044e:	6143      	str	r3, [r0, #20] 
} 
 8000450:	4770      	bx	lr
	...

08000454 <flash_set_ws>: 

void flash_set_ws(u32 ws) 
{ 
	u32 reg32; 

	reg32 = FLASH_ACR; 
 8000454:	4b03      	ldr	r3, [pc, #12]	; (8000464 <flash_set_ws+0x10>) 
 8000456:	681a      	ldr	r2, [r3, #0] 
	reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2)); 
 8000458:	f022 0207 	bic.w	r2, r2, #7
	reg32 |= ws; 
 800045c:	4302      	orrs	r2, r0
	FLASH_ACR = reg32; 
 800045e:	601a      	str	r2, [r3, #0] 
} 
 8000460:	4770      	bx	lr
 8000462:	bf00      	nop
 8000464:	40023c00 	.word	0x40023c00

08000468 <pwr_set_vos_scale>: 

#include <libopencm3/stm32/f4/pwr.h> 

void pwr_set_vos_scale(vos_scale_t scale) 
{ 
	if (scale == SCALE1) 
 8000468:	b928      	cbnz	r0, 8000476 <pwr_set_vos_scale+0xe> 
		PWR_CR |= PWR_CR_VOS; 
 800046a:	4b07      	ldr	r3, [pc, #28]	; (8000488 <pwr_set_vos_scale+0x20>) 
 800046c:	681a      	ldr	r2, [r3, #0] 
 800046e:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 8000472:	601a      	str	r2, [r3, #0] 
 8000474:	4770      	bx	lr
	else if (scale == SCALE2) 
 8000476:	2801      	cmp	r0, #1
 8000478:	d104      	bne.n	8000484 <pwr_set_vos_scale+0x1c> 
		PWR_CR &= PWR_CR_VOS; 
 800047a:	4b03      	ldr	r3, [pc, #12]	; (8000488 <pwr_set_vos_scale+0x20>) 
 800047c:	681a      	ldr	r2, [r3, #0] 
 800047e:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 8000482:	601a      	str	r2, [r3, #0] 
 8000484:	4770      	bx	lr
 8000486:	bf00      	nop
 8000488:	40007000 	.word	0x40007000

0800048c <hse_8mhz_3v3>: 
 800048c:	00f00008 00000502 00000603 01040500     ................
 800049c:	01c9c380 03938700 01500008 00000702     ..........P.....
 80004ac:	00000605 00040500 0280de80 0501bd00     ................

markcomp77

ursus_arctos pisze: więcej widać w libopencm3 niż w oryginalnym CMSIS

dzięki za wsparcie..
ja jak zwykle zagoniony - ale może uda mi sie przez chwilę coś poczytać na temat tej biblioteki...

Kod: Zaznacz cały

mark@hpecik:~$ cd ARM
mark@hpecik:~/ARM$ mkdir libopencm3
mark@hpecik:~/ARM$ cd libopencm3/
mark@hpecik:~/ARM/libopencm3$  git clone git://github.com/libopencm3/libopencm3.git
Cloning into 'libopencm3'...
remote: Counting objects: 8530, done.
remote: Compressing objects: 100% (2760/2760), done.
remote: Total 8530 (delta 5493), reused 8452 (delta 5438) 
Receiving objects: 100% (8530/8530), 1.34 MiB | 850 KiB/s, done.
Resolving deltas: 100% (5493/5493), done.
mark@hpecik:~/ARM/libopencm3$ cd libopencm3/
mark@hpecik:~/ARM/libopencm3/libopencm3$ make
  BUILD   lib/stm32/f1
  CP      libopencm3_stm32f1.ld
  CC      vector.o
  CC      rcc.o
....
  BUILD   examples/lpc43xx/hackrf-jellybean/ssp
  BUILD   examples/lpc43xx/hackrf-jellybean/systick
  BUILD   examples/lm3s/lm3s3748-evb/miniblink

biblioteka łatwo się ściągnęła... i dało się coś kompilować

o!... jest i jakaś dokumentacja i również daje się makeować

zabieram się za oglądanie doc przez html... dzięks:)

[ Dodano: 2012-10-15, 11:49 ]
tak wygląda miganie z libopencm3

Kod: Zaznacz cały

#include <libopencm3/stm32/f4/rcc.h> 
#include <libopencm3/stm32/f4/gpio.h> 

/* Set STM32 to 168 MHz. */
void clock_setup(void) 
{ 
	rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]); 

	/* Enable GPIOD clock. */
	rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN); 
} 

void gpio_setup(void) 
{ 
	/* Set GPIO12-15 (in GPIO port D) to 'output push-pull'. */
	gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT,
			GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15); 
} 

int main(void) 
{ 
	int i; 

	clock_setup(); 
	gpio_setup(); 

	/* Set two LEDs for wigwag effect when toggling. */
	gpio_set(GPIOD, GPIO12 | GPIO14); 

	/* Blink the LEDs (PD12, PD13, PD14 and PD15) on the board. */
	while (1) { 
		/* Toggle LEDs. */
		gpio_toggle(GPIOD, GPIO12 | GPIO13 | GPIO14 | GPIO15); 
		for (i = 0; i < 6000000; i++) /* Wait a bit. */
			__asm__("nop"); 
	} 

	return 0; 
}

markcomp77

ursus_arctos pisze:Hmm... widzę, że koledzy chcą ustawić peryferia "na pałę", bez bibliotek... To się może zemścić. Jeżeli nie podobają się te od ST (w sumie nie dziwię się), to może libopencm3?

hehe... "na pałę"...tak trochę chcemy skumać co i gdzie tam jest w tym stm32
projekt led - blink - to dobra okazja na zrozumienie...

ja to mam jeszcze problem ze skomunikowanie coIDE na Wine z discovery...
samo coIDE poza pewnymi zawieszeniami, właściwie działa dość sprawnie pod Wine/Linux-64b
pozostaje jedynie dorobić jakoś tę komunikację - bo sam plik *.elf daje się przesłać "z ręki" do discovery... ale to nie jest praca interaktywna.. a przydało by się debugowanie w coIDE

markcomp77

fajny opis... dzięks

ta "ręczna" metoda wysyłania binarki do modułu discovery działa, również wysłanie wygenerowanego pliku *.elf przez coIDE - jednak nie udaje mi się tego wysłać z coIDE pod Wine, bo jakoś nie udaje się klientowi stlink w coIDE skomunikować z serverikiem stlink zaimplementowanym pod linuksem (gdbserver/st-util fu bar)

markcomp77

ten mój wcześniejszy blink również się kompiluje pod coIDE

Kod: Zaznacz cały

/* missing type */ 
 typedef unsigned int uint32_t; 


 /* hardware configuration */ 
 #define GPIOD 0x40020C00              /* port D */ 
 #define GPIOD_MODER (GPIOD + 0x00)    /* port mode register */ 
 #define LED_PORT_ODR (GPIOD + 0x14)   /* port output data register */ 
 #define LED_GREEN (1 << 12)           /* port D, pin 12 */ 
 #define LED_ORANGE (1 << 13)          /* port D, pin 13 */ 
 #define LED_RED (1 << 14)             /* port D, pin 14 */ 
 #define LED_BLUE (1 << 15)            /* port D, pin 15 */ 

 void _tmain(void) { 
     main(); 
 } 
 static inline void setup_leds(void) 
 { 
   *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) | 
       (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); 
 } 


 static inline void switch_leds_on(void) 
 { 
   *(volatile uint32_t*)LED_PORT_ODR = LED_BLUE | LED_GREEN | LED_ORANGE | LED_RED; 
 } 

 static inline void switch_leds_off(void) 
 { 
   *(volatile uint32_t*)LED_PORT_ODR = 0; 
 } 

 #define delay()                                    \ 
 do {                                            \ 
   register unsigned int i;                        \ 
   for (i = 0; i < 1000000; ++i)                    \ 
     __asm__ __volatile__ ("nop\n\t":::"memory");\ 
 } while (0) 

 /* static void __attribute__((naked)) __attribute__((used)) main(void) */ 
 void main(void) 
 { 
   setup_leds(); 

   while (1) 
   { 
     switch_leds_on(); 
     delay(); 
     switch_leds_off(); 
     delay(); 
   } 
 }

AOLEK pisze:To może zacznijmy od tego a potem będzie łatwiej

Kod: Zaznacz cały

#define HWREG(x)         (*((volatile unsigned long *)(x))) 
#define RCC             0x40023800 
#define RCC_AHB1ENR     (RCC + 0x30) 
#define GPIOA             0x40020000 
#define GPIOA_IDR        (GPIOA + 0x10) 
#define GPIOD            0x40020c00 
#define GPIOD_MODER     (GPIOD + 0x0) 
#define GPIOD_BSRR      (GPIOD + 0x18) 

#define STACK_TOP 0x20002000

albo jakieś namiary...

dużo na temat symboli typu GPIOx można znaleźć nocie stm32 (mapie pamięci)

np. -- wzięte z noty:

Kod: Zaznacz cały

0x4004 0000 - 0x4007 FFFF USB OTG HS
0x4002 9400 - 0x4003 FFFF Reserved
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF ETHERNET MAC
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF 0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0X4002 5000 - 0X4002 5FFF Reserved
0x4002 4000 - 0x4002 4FFF 
0x4002 3C00 - 0x4002 3FFF Flash interface register
0x4002 3800 - 0x4002 3BFF RCC
0X4002 3400 - 0X4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
0x4002 2400 - 0x4002 2FFF Reserved
0x4002 2000 - 0x4002 23FF GPIOI
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1800 - 0x4002 1BFF GPIOG
0x4002 1400 - 0x4002 17FF GPIOF
0x4002 1000 - 0x4002 13FF GPIOE
0X4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA
0x4001 5800- 0x4001 FFFF Reserved

zazwyczaj symbole typu GPIOx bywają zdefiniowane w #includach

[ Dodano: 2012-10-13, 22:29 ]
http://www.emcu.it/STM32/STM32VLDiscove ... brary.html

tutaj jest nieźle wyjaśnione inicjowanie peryferii...

markcomp77

AOLEK pisze:Teraz trzeba się zagłębiać w biblioteke STM32F4.

to jest temat wart publicznego przedyskutowania...
bo jest z tym niezła bonanza

markcomp77

AOLEK pisze:markcomp77 napisał/a:
muszę poszukać, gdzie się ustawia port...

w opcjach debuggera obok

hehe... szukałem gdzie zmienić port servera, gdy można zmienić port klient

AOLEK pisze:A to co ? po odchaczeniu opcji: autodownload w opcjach debuggera.

debugger łączyć się chce ze sprzętem... anie może, bo go nie podłączyłeś... albo coś jest nie tak z konfiguracją łączenia

Znaleziono 13 wyników

Szyna liniowa HGR15R 0730mm HIWIN

Dysk na rzepy 150 H21N/P806H

Znaleziono 13 wyników

Szyna liniowa HGR15R 0730mm HIWIN

Dysk na rzepy 150 H21N/P806H

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