no... niestety trzeba było przeczytać
http://www.altera.com/literature/ds/acex.pdf 
ACEX 1K Datasheet pisze:ACEX 1K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices, which configure ACEX 1K devices via a serial data stream. Configuration data can also be downloaded from system RAM or via the Altera MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cables. After an ACEX 1K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 40 ms, real-time changes can be made during system operation.
ACEX 1K devices contain an interface that permits microprocessors to configure ACEX 1K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat an ACEX 1K device as memory and configure it by writing to a virtual memory location, simplifying device reconfiguration.
na początku mana piszą:
Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device
co sugeruje, że mamy do czynienia z PLD.. czyli z czymś podobnym do PAL/GAL (ino większym)
ale dalej... to widać, że to fpga...
FPGAs vs. CPLDs pisze:FPGAs are RAM based - they need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based - they are active at power-up (i.e. as long as they've been programmed at least once...).
